- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄34471 > 571FCAFREQDGR (SILICON LABORATORIES) VCXO, CLOCK, 10 MHz - 945 MHz, LVDS OUTPUT PDF資料下載
參數(shù)資料
| 型號： | 571FCAFREQDGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 10 MHz - 945 MHz, LVDS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-8 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大小： | 315K |
| 代理商： | 571FCAFREQDGR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁
Si570/Si571
Rev. 0.31
5
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Voltage1
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
1.8 V option
1.71
1.8
1.89
Supply Current
IDD
Output enabled
LVPECL
CML
LVDS
CMOS
—
120
108
99
90
130
117
108
98
mA
TriState mode
—
60
75
Output Enable (OE)2
VIH
0.75 x VDD
——
V
VIL
——
0.5
Operating Temperature Range
TA
–40
—
85
C
Notes:
1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 21 for further details.
2. OE pin includes a 17 k
Ω pullup resistor to VDD or a 17 kΩ pulldown to GND depending on the OE polarity specified in
the part number. See "7. Ordering Information" on page 21.
Table 2. VC Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Control Voltage Tuning Slope1,2,3
KV
VC 10 to 90% of VDD
—
33
45
90
135
180
356
—
ppm/V
Control Voltage Linearity4
LVC
BSL
–5
±1
+5
%
Incremental
–10
±5
+10
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
ZVC
500
—
k
Ω
Nominal Control Voltage
VCNOM
@ fO
—VDD/2
—
V
Control Voltage Tuning Range
VC
0VDD
V
Notes:
1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 21.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 571JGAFREQDG | VCXO, CLOCK, 10 MHz - 160 MHz, CMOS OUTPUT |
| 571KAAFREQDGR | VCXO, CLOCK, 10 MHz - 945 MHz, CMOS OUTPUT |
| 571MCAFREQDGR | VCXO, CLOCK, 10 MHz - 945 MHz, LVPECL OUTPUT |
| 571TJAFREQDGR | VCXO, CLOCK, 10 MHz - 160 MHz, CMOS OUTPUT |
| 571WJAFREQDGR | VCXO, CLOCK, 10 MHz - 945 MHz, CMOS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 571FCB000107DG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
| 571FCB000109DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ VCXO LVDS 6PIN - Trays |
| 571FCB000117DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 133.3333MHZ VCXO LVDS 8SMD - Trays |
| 571FCB000117DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 133.3333MHZ VCXO LVDS 8SMD - Tape and Reel |
| 571FCB000177DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 297MHZ VCXO LVDS 8SMD - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。