參數(shù)資料
型號: 571EJAFREQDG
廠商: SILICON LABORATORIES
元件分類: VCXO, clock
英文描述: VCXO, CLOCK, 10 MHz - 945 MHz, LVPECL OUTPUT
封裝: ROHS COMPLIANT PACKAGE-8
文件頁數(shù): 18/26頁
文件大?。?/td> 315K
代理商: 571EJAFREQDG
Si570/Si571
Rev. 0.31
25
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
both XO and VCXO.
Updated the Nominal Control Voltage in Table 2, “VC
Updated tables to reflect slight performance
differences between Si570 and Si571.
Added detail to the "3.2. Frequency Programming
Procedure now requires use of two frequency
configuration register sets.
Procedure now recommends disabling output at
powerup to protect equipment not expecting the
default output frequency.
Added second frequency configuration register set
to the register tables.
Added frequency configuration select register.
consistent with the Si55x series devices.
Revision 0.2 to Revision 0.3
Device maintains stable operation over –40 to +85 C
operating temperature range.
Supply current specifications updated.
Updated LVDS differential peak-peak swing
specifications.
Revised period jitter specifications.
page 10 to reflect the soldering temperature time at
260 C is 20–40 sec per JEDEC J-STD-020C.
Updated device programming procedure in Section
Changed ordering instructions to revision D.
Revision 0.3 to Revision 0.31
Corrected Step 6 to read “bit 4”.
Corrected Freeze DCO bit location in Register 137 to
bit 4 on pages 14 and 18.
相關(guān)PDF資料
PDF描述
571JFAFREQDGR VCXO, CLOCK, 10 MHz - 160 MHz, CMOS OUTPUT
571KGAFREQDGR VCXO, CLOCK, 10 MHz - 945 MHz, CMOS OUTPUT
571MHAFREQDG VCXO, CLOCK, 10 MHz - 945 MHz, LVPECL OUTPUT
571NKAFREQDG VCXO, CLOCK, 10 MHz - 945 MHz, LVDS OUTPUT
571PGAFREQDGR VCXO, CLOCK, 10 MHz - 160 MHz, CMOS OUTPUT
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