參數(shù)資料
型號: 554AF000282DG
廠商: SILICON LABORATORIES
元件分類: VCXO, clock
英文描述: VCXO, CLOCK, LVPECL OUTPUT
封裝: ROHS COMPLIANT PACKAGE-8
文件頁數(shù): 9/14頁
文件大小: 238K
代理商: 554AF000282DG
Si554
4
Rev. 0.6
Table 5. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Phase Jitter (RMS)1,2,3
for FOUT > 500 MHz
φ
J
Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
0.26
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
0.27
0.26
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
0.32
0.26
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
0.40
0.27
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
0.49
0.28
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
0.87
0.33
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
相關PDF資料
PDF描述
554AJ000398DG VCXO, CLOCK, LVPECL OUTPUT
554BC000426DGR VCXO, CLOCK, LVDS OUTPUT
554BD000413DG VCXO, CLOCK, LVDS OUTPUT
554DD000129DG VCXO, CLOCK, ECL OUTPUT
554HC000249DGR VCXO, CLOCK, ECL OUTPUT
相關代理商/技術參數(shù)
參數(shù)描述
554AF000282DGR 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/644.53125MHZ/666.51429MHZ/669.32658MHZ - Tape and Reel
554AG000463DGR 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel
554AH000141DG 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays
554AH000141DGR 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel
554AH000260DG 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays