- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄116755 > 552FF000108BGR (SILICON LABORATORIES) VCXO, CLOCK, 693.48299 MHz, LVDS OUTPUT PDF資料下載
參數(shù)資料
| 型號(hào)： | 552FF000108BGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 693.48299 MHz, LVDS OUTPUT |
| 封裝： | ROHS COMPLIANT, SMD, 6 PIN |
| 文件頁(yè)數(shù)： | 23/80頁(yè) |
| 文件大?。?/td> | 3734K |
| 代理商： | 552FF000108BGR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)
Si552
Rev. 0.5
3
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Nominal Frequency1,2,3
fO
LVDS/CML/LVPECL
10
—
945
MHz
CMOS
10
—
160
Temperature Stability1,4
f/fO
TA = –40 to +85 C
–20
–50
–100
—
+20
+50
+100
ppm
Absolute Pull Range1,4
APR
±25
—
±150
ppm
Aging
Frequency drift over
15 year life.
——
±10
ppm
Power up Time5
tOSC
——
10
ms
Settling Time After FS Change
tFRQ
——
10
ms
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by VCNOM =3/8 xVDD.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO (to within ±1 ppm of fO).
Table 4. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVPECL Output Option1
VO
mid-level
VDD – 1.42
—
VDD – 1.25
V
VOD
swing (diff)
1.1
—
1.9
VPP
VSE
swing (single-ended)
0.5
—
0.93
VPP
LVDS Output Option2
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.32
0.40
0.50
VPP
CML Output Option2
VO
mid-level
—
VDD – 0.75
—
V
VOD
swing (diff)
0.70
0.95
1.20
VPP
CMOS Output Option3
VOH
IOH =32mA
0.8 x VDD
—
VDD
V
VOL
IOL =32mA
——
0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
—
350
ps
CMOS with CL = 15 pF
—
1
—
ns
Symmetry (duty cycle)
SYM
LVPECL:
VDD – 1.3 V (diff)
LVDS:
1.25 V (diff)
CMOS:
VDD/2
45
—
55
%
Notes:
1. 50
to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 552GE000032BG | VCXO, CLOCK, 148.5 MHz, CMOS OUTPUT |
| 550AD132M812BGR | VCXO, CLOCK, 132.812 MHz, LVPECL OUTPUT |
| 550AD184M000BGR | VCXO, CLOCK, 184 MHz, LVPECL OUTPUT |
| 550AD311M040BGR | VCXO, CLOCK, 311.04 MHz, LVPECL OUTPUT |
| 550AD622M080BGR | VCXO, CLOCK, 622.08 MHz, LVPECL OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 552FH000328DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 297MHZ/297.7033MHZ VCXO LVDS 6SMD - Trays |
| 552FH000328DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 297MHZ/297.7033MHZ VCXO LVDS 6SMD - Tape and Reel |
| 552FH000383DGR | 制造商:Silicon Laboratories Inc 功能描述:CONTROLLED OSCILLATOR 150MHZ VCXO LVDS 6-PIN SMD - Tape and Reel |
| 552FH000384DGR | 制造商:Silicon Laboratories Inc 功能描述:CONTROLLED OSCILLATOR 10MHZ/150MHZ VCXO LVDS 6-PIN SMD - Tape and Reel |
| 552FJ000260DG | 制造商:Silicon Laboratories Inc 功能描述:CONTROLLED OSCILLATOR 148.35165MHZ/148.5MHZ VCXO LVDS 6-PIN - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。