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參數(shù)資料
| 型號(hào)： | 54SX08-STD |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | 54SX08-STD |
3
G ener a l - P ur pos e S DRAM Cont r o l l er
the SDRAM controller when simple deassertion of
RD/WR_BE_NOW occurs.
From time 120us to 148us, the RD/WR_BE_NOW signals are
driven by a pseudo-random bit stream and vectors are
targeted to cause page crossings for a very complete testing
of the MiniCore.
To run the simulation:
1.
Unzip the SDRAM MiniCore zip file,
2.
Start MTI,
3.
In MTI, File->change directory
"designs/SDRAM/testbench/mti"
4.
In MTI, macro->execute macro "comp.do"
F unc t i ona l W a v e f o r m s
and write. They represent key events. For more detailed
events, run the testbench and view simulation signals.
Figure 2 is a write cycle. Significant events are as follows:
1.
At clock 2, ACTIVE, ADDR and WR_CYC from the user
ask the SDRAM controller to prepare the SDRAM for a
write.
2.
At clock 4, the SDRAM controller asserts WR_BE_NOW
indicating that at cycle 5, the SDRAM will be ready to
accept data.
3.
The user is not ready to transfer data until clock 8.
4.
Data is written into the SDRAM on clocks 8 through 15
except 12 (WR_BE_NOW not asserted during that cycle).
5.
The cycle ends at clock16.
Figure 3, the Read cycle is much like the write cycle except
because of the pipelined nature of an SDRAM. Any time the
user de-asserts the WR_BE_NOW as shown in cycle 5, the
SDRAM controller will become not ready for several clocks
while it reloads the SDRAM data output pipeline.
Figure 2 Write Cycle
Figure 3 Read Cycle
CLK
ACTIVE
ADDR[31:0]
WR_BE_RDY
WR_BE_NOW
CYC_DONE
ADDn
13
14
15
16
56
7
8
910
11
12
3
4
WR_CYC
DATAn
N+1
N+2
N+3
SDRAM DATA IN
N+4
N+5
N+6
CLK
ACTIVE
ADDR[31:0]
RD_BE_RDY
WR_BE_NOW
CYC_DONE
ADDn
13
14
15
16
56
7
8
910
11
12
3
4
WR_CYC
DATAn
N+1
N+2
N+3
N+4
SDRAM DATA
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