參數(shù)資料
型號(hào)： 514JAAXXXXXXAAGR
廠商： SILICON LABORATORIES
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 250 MHz, OTHER CLOCK GENERATOR, PDSO6
封裝： 5 X 7 MM, ROHS COMPILANT PACKAGE-6
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 267K
代理商： 514JAAXXXXXXAAGR
Si514
20
Preliminary Rev. 0.9
Register 11.
Bit
7654
3210
Name
LS_DIV[2:0]
HS_DIV[9:8]
Type
R/W
Default
Varies
Bit
Name
Function
7
Reserved
6:4
LS_DIV[2:0]
Last output divider stage. Used during large frequency changes. To update, follow
large frequency change procedure. LS_DIV value updates asynchronously.
000: divide-by-1
001: divide-by-2
010: divide-by-4
011: divide-by-8
100: divide-by-16
101: divide-by-32
All others reserved.
3:2
Reserved
1:0
HS_DIV[9:8]
Integer divider that divides VCO frequency and provides output to LS-DIV. Follow the
large frequency change procedure when updating. The allowed values are even num-
bers in the range from 10 to 1022 (i.e., 10, 12, 14, 16, ..., 1022). The decimal value
represents the actual divide value (i.e., 12 means divide-by-12).
Register 14.
Bit
7
65
43
2
1
0
Name
OE_STATE[1:0]
Type
R/W
Default
0
Bit
Name
Function
7:6
Reserved
5:4
OE_STATE[1:0]
Sets logic state of output when output disabled.
00: high impedance
10: logic low when output disabled
01: logic high when output disabled
11: reserved
3:0
Reserved
相關(guān)PDF資料
PDF描述
514JAAXXXXXXBAGR 250 MHz, OTHER CLOCK GENERATOR, PDSO6
514JABXXXXXXBAGR 170 MHz, OTHER CLOCK GENERATOR, PDSO6
514JACXXXXXXAAG 125 MHz, OTHER CLOCK GENERATOR, PDSO6
514JBAXXXXXXAAG 250 MHz, OTHER CLOCK GENERATOR, PDSO6
514JBCXXXXXXAAG 125 MHz, OTHER CLOCK GENERATOR, PDSO6
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