- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358638 > 3D7303K-300 (DATA DELAY DEVICES INC) MONOLITHIC TRIPLE FIXED DELAY LINE PDF資料下載
參數(shù)資料
| 型號(hào)： | 3D7303K-300 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 中文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, DIP-14 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 40K |
| 代理商： | 3D7303K-300 |
3D7303
Doc #96001
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
APPLICATION NOTES (CONT’D)
custom reference designator
identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all.
Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7303 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The
thermal coefficient
is reduced to
600
PPM/C
, which is equivalent to a variation , over
the 0C-70C operating range, of
±
3%
from the
room-temperature delay settings and/or
1.0ns
,
whichever is greater. The
power supply
coefficient
is reduced, over the 4.75V-5.25V
operating range, to
±
1%
of the delay settings at
the nominal 5.0VDC power supply and/or
2.0ns
,
whichever is greater.
It is essential that the
power supply pin be
adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
MIN
MAX
30
UNITS
mA
V
V
μ
A
μ
A
mA
NOTES
2.0
0.8
1
1
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
-4.0
Low Level Output Current
I
OL
4.0
mA
Output Rise & Fall Time
T
R
& T
F
2
ns
*I
DD
(Dynamic) = 3 * C
LD
* V
DD
* F
where:
C
= Average capacitance load/line (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 3D7303SERIES | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 3D7303 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7304D-10 | MONOLITHIC QUADRUPLE FIXED DELAY LINE |
| 3D7304 | MONOLITHIC QUADRUPLE FIXED DELAY LINE |
| 3D7304SERIES | MONOLITHIC QUADRUPLE FIXED DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7303K40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7303K-40 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7303K400 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7303K-400 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7303K50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。