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參數(shù)資料
| 型號： | 2SC5907 |
| 英文描述： | Low-Power, Single/Dual-Voltage µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay |
| 文件頁數(shù)： | 4/19頁 |
| 文件大小： | 117K |
| 代理商： | 2SC5907 |
2SC5907
Rev.0, Oct. 2002, page 4 of 19
1.0
0.8
0.6
0.4
0.2
0
0.5
1.0
1.5
2.0
Collector to Base Voltage V
CB
(V)
C
1.0
0.8
0.4
0.2
0
0.5
1.0
1.5
2.0
Collector to Base Voltage V
CB
(V)
R
r
Collector Output Capacitance vs.
Collector to Base Voltage
Reverse Transfer Capacitance vs.
Collector to Base Voltage
20
16
12
8
4
0
1
2
5
10
20
50
100
Collector Current I
C
(mA)
G
T
20
16
12
8
4
0
1
2
5
10
20
50
100
Gain Bandwidth Product vs.
Collector Current
f = 900 MHz
f = 1 GHz
I
E
= 0
f = 1 MHz
Emitter ground
f = 1 MHz
V
CE
= 3 V
1 V
V
CE
= 3 V
0.6
2 V
P
Power Gain vs. Collector Current
Collector Current I
C
(mA)
1 V
2 V
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