
440
Evaluating and Programming the 29K RISC Family
Figure 8-8.
29K Microprocessors Running the LAPD Benchmark
with
25 MHz Memory
Systems
0
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
Am29030 D=3/2
Am29030 D=3/1
Am29030 S=3/2
Am29030 D=2/1
Am29050 D=3/2
Am29030 S=2/1
Am29050 D=2/1
Am29040 D=3/2
Am29040 S=3/2
Am29040 D=3/1
Am29040 D=2/1
Am29040 S=2/1
32–bit memory
32–bit memory at 1/2 CPU speed
Packets per second
S=SRAM
D=DRAM
Memory access
I=2/1, D=3/2
I=2/1, D=2/1
upgrade path
60 ns DRAM. Concluding, a fast (and relatively expensive) DRAM may achieve 2/1
access using an Am29040. However, to improve timing margins the operating
frequency may have to be dropped a little below 25 MHz. If fast DRAM can not be
supported by the allocated system budget, then a 3/2 DRAM system or an interleaved
3/1 DRAM system is more appropriate.