參數(shù)資料
型號: 28LV64
元件分類: EEPROM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 6/12頁
文件大小: 527K
代理商: 28LV64
CAT28LV64
6
Doc. No. 1010, Rev. D
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN
DATA VALID
HIGH-Z
tCS
tAH
tCH
tWC
tOEH
tBLC
tDH
tDS
tOES
tWP
Byte Write
A write cycle is executed when both
CE
and
WE
are low,
and
OE
is high. Write cycles can be initiated using either
WE
or
CE
, with the address input being latched on the
falling edge of
WE
or
CE
, whichever occurs last. Data,
conversely, is latched on the rising edge of
WE
or
CE
,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
Figure 4. Byte Write Cycle [WE Controlled]
DEVICE OPERATION
Read
Data stored in the CAT28LV64 is transferred to the data
bus when
WE
is held high, and both
OE
and
CE
are held
low. The data bus is set to a high impedance state when
either
CE
or
OE
goes high. This 2-line control architecture
can be used to eliminate bus contention in a system
environment.
ADDRESS
CE
OE
WE
tRC
DATA OUT
DATA VALID
DATA VALID
tCE
tOE
tOH
tAA
tOHZ
tHZ
VIH
HIGH-Z
tLZ
tOLZ
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