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| 型號： | 21084 |
| 英文描述： | AMD-K6 Processor Bios Design Application Note AMD-K6 Processor I/O Model Application Note |
| 中文描述： | 的AMD - K6處理器的BIOS設(shè)計中的應(yīng)用注意的AMD - K6處理器的I / O模型的應(yīng)用說明 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 357K |
| 代理商： | 21084 |
IBIS Modeling
5
21084D/0—June 1999
AMD-K6
Processor I/O Model
Figure 3 illustrates the timings that must be considered when
determining whether the hold time of a signal is met. The
timings are defined as follows:
I
T
period
is the period of the system clock
T
skew
is the maximum clock skew between the clock that
launches a signal (solid-line clock) and the clock that
captures a signal (dashed-line clock)
T
jitter
(not shown in Figure 3) is the maximum variance
allowance between successive periods of the system clock
T
validmin
is the minimum valid delay of a signal from its
source
T
propmin
is the minimum propagation delay of the signal
along the PCB trace from its source to its destination. This
delay is obtained by simulating with the best-case
conditions.
T
holdmin
is the minimum required hold time of a signal at its
destination
I
I
I
I
I
Figure 3. Timing Considerations to Meet Hold Time
Signal at Destination
Signal at Source
Clocks
T
period
T
skew
T
propmin
T
validmin
T
holdmin
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