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參數(shù)資料
| 型號： | 11274-502-XTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 28 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 746K |
| 代理商： | 11274-502-XTD |
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14
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
A
W
S
P
START
Command
WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge
From bus host
to device
From device
to bus host
7-bit Receive
Device Address
DEVICE ADDRESS
A
REGISTER ADDRESS
DATA
Figure 15: Sequential Register Write Procedure
A
W
S
START
Command
WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge
READ Command
NO Acknowledge
From bus host
to device
From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS
A
REGISTER ADDRESS
A
R
A P
S
DEVICE ADDRESS
DATA
Repeat START
Figure 16: Sequential Register Read Procedure
A
DATA
W A
From bus host
to device
S
REGISTER ADDRESS
P
From device
to bus host
DEVICE ADDRESS
Register Address
Acknowledge
STOP Condition
Data
Acknowledge
START
Command
WRITE Command
7-bit Receive
Device Address
Figure 13: Random Register Write Procedure
A
R
A
W
S
REGISTER ADDRESS
P
S
DEVICE ADDRESS
START
Command
WRITE Command
Acknowledge
Register Address
Acknowledge
READ Command
Acknowledge
Data
NO Acknowledge
STOP Condition
From bus host
to device
From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS
DATA
Repeat START
Figure 14: Random Register Read Procedure
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