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    參數(shù)資料
    型號(hào): 1027PE-42TE13
    元件分類: 電源管理
    英文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8
    封裝: PLASTIC, DIP-8
    文件頁數(shù): 2/17頁
    文件大小: 108K
    代理商: 1027PE-42TE13
    10
    CAT1026, CAT1027
    Preliminary Information
    Doc. No. 3010, Rev. E
    ACKNOWLEDGE
    After a successful data transfer, each receiving device
    is required to generate an acknowledge. The
    acknowledging device pulls down the SDA line during
    the ninth clock cycle, signaling that it received the 8 bits
    of data.
    The CAT1026 and CAT1027 respond with an
    acknowledge after receiving a START condition and its
    slave address. If the device has been selected along
    with a write operation, it responds with an acknowledge
    after receiving each 8-bit byte.
    When the CAT1026 and CAT1027 begin a READ mode
    it transmits 8 bits of data, releases the SDA line and
    monitors the line for an acknowledge. Once it receives
    this acknowledge, the CAT1026 and CAT1027 will
    continue to transmit data. If no acknowledge is sent by
    the Master, the device terminates data transmission and
    waits for a STOP condition.
    WRITE OPERATIONS
    Byte Write
    In the Byte Write mode, the Master device sends the
    START condition and the slave address information (with
    the R/
    W bit set to zero) to the Slave device. After the Slave
    generates an acknowledge, the Master sends a 8-bit
    address that is to be written into the address pointers of
    the device. After receiving another acknowledge from the
    Slave, the Master device transmits the data to be written
    into the addressed memory location. The CAT1026 and
    CAT1027 acknowledge once more and the Master
    generates the STOP condition. At this time, the device
    begins an internal programming cycle to non-volatile
    memory. While the cycle is in progress, the device will not
    respond to any request from the Master device.
    Figure 8. Slave Address Bits
    CAT
    Default Configuration
    1
    010
    0
    R/W
    START BIT
    SDA
    STOP BIT
    SCL
    Figure 6. Start/Stop Timing
    ACKNOWLEDGE
    1
    START
    SCL FROM
    MASTER
    89
    DATA OUTPUT
    FROM TRANSMITTER
    DATA OUTPUT
    FROM RECEIVER
    Figure 7. Acknowledge Timing
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