and it is not referenced to ana" />
參數(shù)資料
型號： 101-1218
廠商： Rabbit Semiconductor
文件頁數(shù)： 73/130頁
文件大?。?/td> 0K
描述： KIT APPLCTN RABBITCORE RCM4010
標(biāo)準(zhǔn)包裝： 1
系列： RabbitCore®
主要目的： *
嵌入式： *
已用 IC / 零件： RCM4010
主要屬性： *
次要屬性： *
已供物品： 板，模塊，250GB 網(wǎng)絡(luò)驅(qū)動器，線纜，CD，電源
其它名稱： 316-1156
User’s Manual
41
If a device such as a battery is
connected across two channels
for a differential measurement,
and it is not referenced to
analog ground, then the current
from the device will flow
through both sets of attenuator
resistors as shown in Figure 11.
This will generate a negative
voltage at one of the inputs,
LN1, which will almost cer-
tainly lead to inaccurate A/D
conversions. To make such dif-
ferential measurements, connect the R1 resistors to the A/D converter’s internal reference
voltage, which is software-configurable for 1.15 V, 2.048 V, or 2.5 V. This internal reference
voltage is available on pin 49 of header J3 as VREF, and allows you to convert analog
input voltages that are negative with respect to analog ground.
NOTE: The amplifier inside the A/D converter’s internal voltage reference circuit has a
very limited output-current capability. The internal buffer can source up to 20 mA and
sink only up to 200 A. Use a separate buffer amplifier if you need to supply any load
current.
The A/D converter’s CONVERT pin is available on pin 48 of header J3 and can be used as
a hardware means of forcing the A/D converter to start a conversion cycle. The CONVERT
signal is an edge-triggered event and has a hold time of two CCLK periods for debounce.
A conversion is started by an active (rising) edge on the CONVERT pin. The CONVERT
pin must stay low for at least two CCLK periods before going high for at least two CCLK
periods. Figure 12 shows the timing of a conversion start. The double falling arrow on
CCLK indicates the actual start of the conversion cycle.
Figure 12. Timing Diagram for Conversion Start Using CONVERT Pin
Appendix B explains the implementation examples of these features on the Prototyping
Board.
Figure 11. Current Flow from Ungrounded
or Floating Source
R5
R6
2.2 nF
R14
R13
2.2 nF
ADC
AIN0
AIN1
+
I
LN0
LN1
+
-
Device
CCLK
BUSY
CONV
Conversion starts
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