參數(shù)資料
型號(hào)： 101-0602
廠商： Rabbit Semiconductor
文件頁(yè)數(shù)： 32/106頁(yè)
文件大小： 0K
描述： COMPUTER SNGL BRD BL2500 44.2MHZ
標(biāo)準(zhǔn)包裝： 10
系列： SBC
模塊/板類型： 單板計(jì)算機(jī)模塊
適用于相關(guān)產(chǎn)品： BL2500
User’s Manual
25
Pulse-width modulation (PWM) is used for the D/A conversion. The digital signal, which
is either 0 V or 3.3 V, will be a train of pulses. This means that if the signal is taken to be
usually at 0 V (or ground), the pulses will be some 3.3 V pulses of varying width. The
voltage will be 0 V for a given time, then jump to 3.3 V for a given time, then back to
ground for a given time, then back to 3.3 V, and so on. A hardware filter that consists of a
resistor and capacitor averages the 3.3 V signal and the 0 V signal over time. Therefore, if
the time that the signal is at 3.3 V is equal to the time the signal is 0 V, the duty cycle will
be 50%, and the average signal will be 1.65 V. If the time at 3.3 V is only 25% of the time,
then the average voltage will be 0.825 V. Thus, the software needs to only vary the time
the signal is at 3.3 V with respect to the time the signal is at 0 V to achieve any desired
voltage between 0 and 3.3 V. It is very easy to do pulse-width modulation with the Rabbit
3000 microprocessor because the chip’s architecture includes an advanced PWM feature.
3.4.2.1 DA0 and DA1
The RC networks supporting DA0 and DA1 converts pulse-width modulated signals to an
analog voltage between 0 V and 3.3 V. A digital signal that varies with time is fed from
PF6 or PF7. The resolution of the DA0 or DA1 output depends on the smallest increment
of time to change the on/off time (the time between 3.3 V and 0 V). The Coyote uses the
Rabbit 3000’s Port F control registers to clock out the signal at a timer timeout. The dedi-
cated PWM hardware has 10 bits of resolution, and so that the voltage can be varied in
1/1024 increments. The resolution is thus about 3 mV (3.3 V/1024).
R6 and R13 are present solely to balance the op amp input current bias. R4 and R15 help
to achieve a voltage close to ground for a 0% duty cycle.
A design constraint dictates how fast the PWM hardware must run. The hardware filter
has a resistor-capacitor filter that averages the 0 V and 3.3 V values. Its effect is to smooth
out the digital pulse train. It cannot be perfect, and so there will be some ripple in the output
voltage. The maximum signal decay between pulses will occur when DA1 is set to 1.65 V.
This means the pulse train will have a 50% duty cycle. The maximum signal decay will be
where RC = 2.5 ms, and t is the pulse on or off time (not the length of the total cycle).
The PWM hardware is driven at the Rabbit 3000 frequency divided by 2. The frequency
achievable with a 29.4 MHz clock is (29.4 MHz/2)/1024 = 14.3 kHz. Since the Rabbit 3000
PWM spreader enhances the frequency fourfold, the effective frequency becomes 57.4 kHz.
This is a period of 1/f = 17.4 s. For a 50% duty cycle, half of the period will be high (8.7
s at 3.3 V), and half will be low (8.7 s at 0 V). Thus, a 29.4 MHz Coyote has t = 8.7 s.
1.65 V
1
e
t
–
RC
--------
–
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