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| 型號： | 01AL |
| 英文描述： | 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER |
| 中文描述： | 2:1差分至的LVPECL復用器 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 301K |
| 代理商： | 01AL |
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
10
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50
Ω transmission lines. Matched imped-
FIGURE 3B. LVPECL OUTPUT TERMINATION
FIGURE 3A. LVPECL OUTPUT TERMINATION
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
INPUTS:
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1k
Ω resistor can
be tied from PCLK to ground.
RECOMMENDATIONS FOR UNUSED INPUT PINS
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