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CHAPTER 18 SERIAL INTERFACE (IIC0) (
μ
PD780024Y, 780034Y SUBSERIES ONLY)
18.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected
to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
data matches the data values stored in the slave address register (SVA0). If the address data matches the SVA0
values, the slave device is selected and communicates with the master device until the master device transmits a
start condition or stop condition.
Figure 18-9. Address
Address
SCL0
1
SDA0
INTIIC0
Note
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R/W
Note
INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
The slave address and the eighth bit, which specifies the transfer direction as described in “
18.5.3
Transfer
direction specification
” below, are together written to the IIC shift register (IIC0) and are then output. Received
addresses are written to IIC0.
The slave address is assigned to the high-order 7 bits of IIC0.
18.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this
transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting data to a slave
device. When the transfer direction specification bit has a value of “1”, it indicates that the master device is receiving
data from a slave device.
Figure 18-10. Transfer Direction Specification
SCL0
1
SDA0
INTIIC0
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R/W
Transfer direction specification
Note
Note
INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.