參數(shù)資料
型號(hào): μPD789187
廠商: NEC Corp.
英文描述: 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述: 8位單片機(jī)微控制器(8位單片微控制器)
文件頁(yè)數(shù): 80/146頁(yè)
文件大小: 630K
代理商: ΜPD789187
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Preliminary Product Information
80
μ
PD789186, 789187, 789196, 789197
Figure 6-38. SMB Control Register 0 Format (2/4)
WTIM0
0
1
The setting of this bit becomes invalid during address transmission, and becomes effective at the end of
transmission. During operation as master, a wait is inserted at the falling edge of the 9th clock during address
transmission. A slave that receives a local address enters the wait status at the falling edge of the 9th clock
after generation of an acknowledge. A slave that receives an extension code enters the wait status at the
falling edge of the 8th clock.
Clear conditions (WTIM0 = 0)
Note
Cleared with instruction
Cleared by RESET input
Set conditions (WTIM0 = 1)
Set with instruction
Wait and interrupt request generation control
Generates interrupt request at falling edge of 8th clock.
In case of master:
Waits with clock output at low level after 8 clocks have been output.
In case of slave:
Waits master with clock set to low level after 8 clocks have been input.
Generates interrupt request at falling edge of 9th clock.
In case of master:
Waits with clock at low level after 9 clocks have been output.
In case of slave:
Waits master with clock set at low level after 9 clocks have been input.
ACKE0
0
1
Clear conditions (ACKE0 = 0)
Note
Cleared with instruction
Cleared by RESET input
Set conditions (ACKE0 = 1)
Set with instruction
Acknowledge control
Acknowledge disabled.
Acknowledge enabled. SDA0 line set to low level during 9 clocks. However, invalid during address
transmission, and valid when EXC0 = 1.
Note
This flag's signals are made invalid by setting SMBE0 = 0.
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