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Preliminary Product Information
58
μ
PD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-28. Block Diagram of A/D Converter
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Sample-and-hold circuit
Voltage comparator
Control
circuit
Successive
approximation
register (SAR)
3
A/D conversion result
register 0 (ADCR0)
T
S
AV
SS
INTAD
A/D conveter mode register 0
(ADM0)
A/D input selection register 0
(ADS0)
Internal bus
AV
SS
ADCS0
0
FR02 FR01 FR00
0
0
0
ADS02ADS01ADS00
AV
REF
AV
DD
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the serial resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to the A/D conversion result register.
(2) A/D conversion result register 0 (ADCR0)
The ADCR holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into the ADCR0.
For the
μ
PD789166Y and
μ
PD789167Y (featuring 8-bit A/D converters), the value of ADCR0 is read using an
8-bit memory manipulation instruction.
For the
μ
PD789176Y and
μ
PD789177Y (featuring 10-bit A/D converters), the value of ADCR0 is read using a
16-bit memory manipulation instruction.
A RESET input makes ADCR0 undefined.
Caution
When 8-bit A/D converters are used (for the
μ
PD789166Y and
μ
PD789167Y), this register
can be accessed only in 8-bit mode. In this case, the address is assumed to be FF15H.
When 10-bit A/D converters are used (for the
μ
PD789176Y and
μ
PD789177Y), this register
can be accessed only in 16-bit mode.
When the
μ
PD78F9177Y is used as flash memory for the
μ
PD789166Y or
μ
PD789167Y,
8-bit access is allowed. However, only those object files generated by an assembler used
with the
μ
PD789166Y or
μ
PD789167Y are supported for this access.