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CHAPTER 4 CLOCK GENERATOR
4.5 Clock Generator Operations
The clock generator generates the following types of clocks and controls the CPU operating mode including
the standby mode.
Main system clock (f
XX
)
Subsystem clock (f
XT
)
CPU clock (f
CPU
)
Clock to peripheral hardware
The following clock generator functions and operations are determined with the standby control register (STBC)
and the oscillation mode selection register (CC).
(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (160 ns when operated
at 12.5 MHz) is selected (STBC = 04H, CC = 00H). Main system clock oscillation stops while low level is
applied to the RESET pin.
(b) With the main system clock selected, one of the six CPU clock types (160 ns, 320 ns, 640 ns, 1280 ns, 2560
ns @ 12.5 MHz) can be selected by setting the STBC and CC.
(c) With the main system clock selected, two standby modes, the STOP mode and the HALT mode, are available.
To decrease current consumption in the STOP mode, the subsystem clock feedback resistor can be
disconnected to stop the subsystem clock with bit 7 (SBK) of STBC, when the system does not use a subsystem
clock.
(d) STBC can be used to select the subsystem clock and to operate the system with low current consumption
(61
m
s when operated at 32.768 kHz).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with STBC. The HALT mode
can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.)
(f)
The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied
to the 16-bit timer/counter, the watch timer, and clock output functions only. Thus, the 16-bit timer/counter
(when watch timer output is selected for count clock during operation with a subsystem clock), the watch
function, and the clock output function can also be continued in the standby state. However, since all other
peripheral hardware operate with the main system clock, the peripheral hardware (except external input clock
operation) also stops if the main system clock is stopped.