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參數(shù)資料
| 型號： | μPD784038 |
| 廠商： | NEC Corp. |
| 英文描述： | 8/16 Bit Single Chip Microcontrollers(8/16位單片微控制器) |
| 中文描述： | 8 / 16位單片機微控制器（8 / 16位單片微控制器） |
| 文件頁數(shù)： | 48/98頁 |
| 文件大小： | 650K |
| 代理商： | ΜPD784038 |
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μ
PD784035, 784036, 784037, 784038
48
Table 9-2. Interrupt Sources
Type
Default
Source
Internal/
Macro
priority
Name
Trigger
external
service
Software
-
BRK instruction
Instruction execution
-
-
BRKCS instruction
Operand error
When the MOV STBC,#byte, MOV WDM,#byte, or LOCATION
instruction is executed, exclusive OR of the byte operand and byte
does not produce FFH.
Nonmaskable
-
NMI
Detection of edge input on the pin
External
-
WDT
Watchdog timer overflow
Internal
Maskable
0 (highest)
INTP0
Detection of edge input on the pin
(TM1/TM1W capture trigger, TM1/TM1W event counter input)
External
Enabled
1
INTP1
Detection of edge input on the pin
(TM2/TM2W capture trigger, TM2/TM2W event counter input)
2
INTP2
Detection of edge input on the pin
(TM2/TM2W capture trigger, TM2/TM2W event counter input)
3
INTP3
Detection of edge input on the pin
(TM0 capture trigger, TM0 event counter input)
4
INTC00
TM0-CR00 match signal issued
Internal
Enabled
5
INTC01
TM0-CR01 match signal issued
6
INTC10
TM1-CR10 match signal issued (in 8-bit operation mode)
TM1W-CR10W match signal issued (in 16-bit operation mode)
7
INTC11
TM1-CR11 match signal issued (in 8-bit operation mode)
TM1W-CR11W match signal issued (in 16-bit operation mode)
8
INTC20
TM2-CR20 match signal issued (in 8-bit operation mode)
TM2W-CR20W match signal issued (in 16-bit operation mode)
9
INTC21
TM2-CR21 match signal issued (in 8-bit operation mode)
TM2W-CR21W match signal issued (in 16-bit operation mode)
10
INTC30
TM3-CR30 match signal issued (in 8-bit operation mode)
TM3W-CR30W match signal issued (in 16-bit operation mode)
11
INTP4
Detection of edge input on the pin
External
Enabled
12
INTP5
Detection of edge input on the pin
13
INTAD
A/D converter processing completed (ADCR transfer)
Internal
Enabled
14
INTSER
ASI0 reception error
-
15
INTSR
ASI0 reception completed or CSI1 transfer completed
Enabled
INTCSI1
16
INTST
ASI0 transmission completed
17
INTCSI
CSI0 transfer completed
18
INTSER2
ASI2 reception error
-
19
INTSR2
ASI2 reception completed or CSI2 transfer completed
Enabled
INTCSI2
20 (lowest)
INTST2
ASI2 transmission completed
Remark
ASI: Asynchronous serial interface
CSI: Synchronous serial interface
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