參數(shù)資料
型號: μPD784036(A)
廠商: NEC Corp.
英文描述: 8/16 Bit Single Chip Microcontrollers(8/16 位單片微控制器)
中文描述: 8 / 16位單片機微控制器(8 / 16位單片微控制器)
文件頁數(shù): 70/90頁
文件大小: 402K
代理商: ΜPD784036(A)
μ
PD784035(A), 784036(A)
70
CLOCK OUTPUT OPERATION
Remarks
n: Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16)
T: t
CYK
(system clock cycle time)
OTHER OPERATIONS
Remarks
t
CYSMP
: Sampling clock set by software
t
CYCPU
: CPU operation clock set by software in the CPU
Unit
μ
s
μ
s
ns
ns
ns
ns
μ
s
μ
s
μ
s
μ
s
Parameter
NMI low-level width
NMI high-level width
INTP0 low-level width
INTP0 high-level width
Low-level width for INTP1-
INTP3 and CI
High-level width for INTP1-
INTP3 and CI
Low-level width for INTP4 and
INTP5
High-level width for INTP4 and
INTP5
RESET low-level width
RESET high-level width
Symbol
t
WNIL
t
WNIH
t
WIT0L
t
WIT0H
t
WIT1L
t
WIT1H
t
WIT2L
t
WIT2H
t
WRSL
t
WRSH
MIN.
10
10
4t
CYSMP
4t
CYSMP
4t
CYCPU
4t
CYCPU
10
10
10
10
MAX.
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
CLKOUT cycle time
CLKOUT low-level width
CLKOUT high-level width
CLKOUT rise time
CLKOUT fall time
MIN.
nT
0.5t
CYCL
- 10
0.5t
CYCL
- 20
0.5t
CYCL
- 10
0.5t
CYCL
- 20
MAX.
10
20
10
20
Conditions
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
Symbol
t
CYCL
t
CLL
t
CLH
t
CLR
t
CLF
相關PDF資料
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