參數(shù)資料
型號(hào)： μPD780973(A)
廠商： NEC Corp.
元件分類： 8位微控制器
英文描述： 8 Bit Single Chip Microcontrollers
中文描述： 8位單片機(jī)微控制器
文件頁數(shù)： 40/52頁
文件大?。?/td> 315K
代理商： ΜPD780973(A)
40
m
PD780973(A)
A/D Converter Characteristics (T
A
= –40 to +85 °C, AV
DD
= V
DD
= 4.5 to 5.5 V, AV
SS
= V
SS
=0 V, f
X
= 8.38 MHz)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Resolution
8
bit
Overall error
Note
±0.6
%
Conversion time
t
CONV
19.1
m
s
Analog input voltage
V
IAN
AV
SS
AV
REF
V
Reference voltage
AV
REF
4.5
V
DD
V
AV
REF
–AV
SS
resistance
R
AIREF
When bit 7 (ADCS1) of the A/D converter
mode register (ADM1) is set to 0.
21.4
k
W
Note
Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
EEPROM Characteristics (T
A
= –40 to +85 °C, AV
DD
= V
DD
= 4.5 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
EEPROM write time
t
EEWR
f
X
= 5.12 MHz
3.4
ms
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T
A
= –40 to +85 °C)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Data retention supply voltage
V
DDDR
2.0
5.5
V
Data retention supply current
disconnected
I
DDDR
V
DDDR
= 2.0 V
0.1
10
m
A
Release signal set time
t
SREL
0
m
s
Oscillation stabilization wait time
t
WAIT
Release by RESET
2
17
/f
X
ms
Release by interrupt request
Note
ms
Note
In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS),
selection of 2
12
/f
X
and 2
14
/f
X
to 2
17
/f
X
is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
V
DDDR
t
SREL
STOP Instruction Execution
t
WAIT
V
DD
RESET
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