
33
CHAPTER 1 GENERAL
Table 1-13. Functional Outline of
μ
PD780924 Subseries
Part Number
Item
Mask ROM
Flash memory
8K bytes
16K bytes
24K bytes
32K bytes
32K bytes
Note
512 bytes
1024 bytes
1024 bytes
Note
64K bytes
8 bits
×
8
×
4 banks
0.24
μ
s/0.48
μ
s/0.96
μ
s/1.9
μ
s/3.8
μ
s (with system clock of 8.38 MHz)
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
Total
CMOS input
CMOS I/O
(On-chip pull-up resistor ON/OFF selected by software : 39)
: 47
: 8
: 39
8 bits
×
1 or 4 bits
×
2
8-bit resolution
×
8 channels
Low-voltage operation : AV
DD
= 2.7 to 5.5 V
UART mode : 2 channels
8-bit timer/event counter
10-bit inverter control timer : 1 channel
Watchdog timer
: 3 channels
: 1 channel
9 (8-bit PWM output: 3, inverter control output: 6)
Internal: 12, external: 4
Internal: 1
1
V
DD
= 2.7 to 5.5 V
T
A
= –40 to +85
°
C
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14
×
14 mm)
Note
The capacities of the flash memory and internal high-speed RAM can be changed by using a memory size
select register (IMS).
Caution The
μ
PD780924 subseries is under development.
ROM
High-speed RAM
Memory space
General-purpose register
Minimum instruction
execution time
Instruction set
I/O port
Real-time output port
A/D converter
Serial interface
Timer
Timer output
Vectored
Maskable
interrupt
Non-maskable
source
Software
Supply voltage
Operating temperature
Package
Internal
memory
μ
PD780921
μ
PD780922
μ
PD780923
μ
PD780924
μ
PD78F0924