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參數(shù)資料
| 型號(hào)： | μPD780823 |
| 廠商： | NEC Corp. |
| 英文描述： | 8 Bit Microcontrollers(8 位微控制器) |
| 中文描述： | 8位微控制器（8位微控制器） |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 36K |
| 代理商： | ΜPD780823 |
The heart of the 78K0 family is a powerful 8-bit CPU. The 0.35 mm process technology ensures
an excellent power/performance ratio. Four 8-bit register banks can be concatenated to a 16-bit
register to support 16-bit operation, eg, 8-bit multiplication with a 16-bit result or 16-bit index
addressing. The 64-Kbyte linear address space is accessed via 16-bit addresses. Bit
manipulation operations are supported on all registers and the entire RAM address space.
Subclock CPU operation to reduce system power consumption is also supported.
With its minimized circuit design, NEC’s DCAN module is an ideal solution for providing full
hardware support for most stand-alone CAN communication applications. Transmission is
supported by two independent transmit buffers with easy priority control. With up to 16
mailboxes in the communication RAM, the receive path provides virtually “Full CAN”
performance. The expansion RAM is used as CAN data RAM to the CPU. The number of
mailboxes for transmission and CAN can be configured by setting the DCAN’s SFR registers.
Each message buffer allocates 16 bytes of expansion RAM, resulting in a RAM requirement of
maximum 288 bytes for the DCAN module.
The converter has 8 channels with 8-bit resolution. One of the channels can be used as a failure
detector that generates an internal interrupt on recognizing an analog input above/below a
certain voltage. The 8-bit conversion time per channel is typically below 18 μs at 8 MHz. The A/D
resistor chain can be switched off to reduce power consumption.
The serial interface includes one UART (Universal Asynchronous Receiver Transmitter) that
supports transfer rates up to 125 kbps. A dedicated baud rate generator sets the transfer rate. A
3-wire CSI (Clocked Serial Interface) for transfer rates up to 1.25 Mbps is also provided. An I
2
C
bus system can be configured using the 2-wire CSI.
A flexible timer offers a total of 6 timer channels. Two-channel 16-bit timers can be used to
generate a basic time interval, for PWM with compare registers and for precise measurements
with up to three 16-bit capture registers. Two-channel 8-bit timers can be used as interval timers,
for PWM output and as external event counters. The watch timer generates a watch time and
can be used simultaneously as an interval timer. The on-chip watchdog timer monitors the CPU
and generates either an internal reset or a non-maskable interrupt. It can also be used as an
additional interval timer if the watchdog function is not required.
The subclock is driven by an external RC connected to the CL1/CL2 terminal pair. This is a very
inexpensive method of generating a low frequency for much lower power consumption in
subclock mode.
The LCD controller/driver can drive up to 160 LCD segments (40 segments, 4 commons).All
LCD segments are shared with ports and can be selected bitwise to ensure maximum port pin
availability if the application does not require all LCD segments.
The sound generator produces sounds composed of a frequency output and a PWM signal for
volume control. The generated frequency is in the range of 256 Hz to 7.7 kHz. It can be used for
simple alarm sounds, like buzzer gong and beeper.
External access can be used to expand memory capacity or to connect external circuits using a
parallel interface.
Functional Block Description
CPU
DCAN Module
Serial Interface
Timer
LCD Driver
RC Subclock
A/D Converter
Sound Generator
External Access
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