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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
μ
PD780058 Subseries)
(11) SBI mode precautions
(a) Slave selection/non-selection is detected by match detection of the slave address received after bus
release (RELD = 1).
For this match detection, match interrupt request (INTCSI0) of the address to be generated with WUP
= 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP =
1.
(b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of
transmission/reception of the command preset by program instead of using the address match detection
method.
(c) In the SBI mode, the BUSY signal is output until the next serial clock falls after a command that resets
the BUSY signal has been issued. If WUP is set to 1 during this period by mistake, the BUSY signal is
not reset. Therefore, be sure to confirm that the SB0 (SB1) pin has gone high after resetting the BUSY
signal, by setting WUP to 1.
(d) For pins that are to be used for data input/output, be sure to carry out the following settings before serial
transfer of the 1st byte after RESET input.
<1>
Set the P25 and P26 output latches to 1.
<2>
Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
<3>
Reset the P25 and P26 output latches from 1 to 0.
(e) The transition of the SB0 (SB1) line from low to high or from high to low when the SCK0 line is high is
recognized as a bus release signal or a command signal, respectively. If the transition timing of the bus
is shifted due to the influence of board capacitance, transmitted data may be judged as a bus release
signal (or a command signal). Exercise care in wiring so that noise is not superimposed on the signal
lines.