170
CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE
Figure 8-12. Format of Interrupt Timing Specification Register (
μ
PD78002Y, 78014Y subseries) (1/2)
R/W
WAT1 WAT0
Controls wait and interrupt processing request
0
0
Generates interrupt request at rising edge of 8th clock of SCK0 (clock output goes into
high-impedance state)
0
1
Setting prohibited
1
0
Used in I
2
C bus mode (8-clock wait).
Generates interrupt processing request at rising edge of 8th clock of SCL (master makes
SCL output low and waits after outputting 8 clocks. Slave makes SCL pin low and requests
for wait after inputting 8 clocks).
1
1
Used in I
2
C bus mode (9-clock wait).
Generates interrupt processing request at rising edge of 9th clock of SCL (master makes
SCL output low and waits after outputting 9 clocks. Slave makes SCL pin low and requests
for wait after inputting 9 clocks).
R/W WREL
Controls wait release
0
Wait release status
1
Releases wait status.
After wait status has been released, this bit is automatically cleared to 0 (used to release wait status
set by WAT1 and WAT0)
R/W
CLC
Controls clock level
Note 2
0
Used in I
2
C bus mode.
Makes output level of SCL pin low when serial transfer is not executed
1
Used in I
2
C bus mode.
Makes output level of SCL pin high impedance when serial transfer is not executed (clock line goes
high).
Used by master to generate start/stop condition.
Notes 1.
Bit 6 (CLD) is a read-only bit.
2.
Clear CLC to 0 when the I
2
C bus mode is not used.
7
6
5
4
3
2
Symbol
1
0
FF63H
WAT0
SINT
WAT1
CLC
WREL
SVAM
SIC
CLD
0
Address
At reset
R/W
00H
R/W
Note 1