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CHAPTER 18 SERIAL INTERFACE (IIC0) (
μ
PD780024Y, 780034Y SUBSERIES ONLY)
Figure 18-4. IIC Status Register (IICS0) Format (2/3)
COI0
Detection of matching addresses
0
Addresses do not match.
1
Addresses match.
Condition for clearing (COI0 = 0)
Condition for setting (COI0 = 1)
When a start condition is detected
When a stop condition is detected
Cleared by LREL0 = 1
When IICE0 changes from 1 to 0
When RESET is input
When the received address matches the local
address (SVA0)
(set at the rising edge of the eighth clock).
TRC0
Detection of transmit/receive status
0
Receive status (other than transmit status). The SDA0 line is set for high impedance.
1
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the rising edge of the first byte’s ninth clock).
Condition for clearing (TRC0 = 0)
Condition for setting (TRC0 = 1)
When a stop condition is detected
Cleared by LREL0 = 1
Master
When a start condition is generated
When IICE0 changes from 1 to 0
Cleared by WREL0 = 1
When ALD0 changes from 0 to 1
When RESET is input
Master
When “1” is output to the first byte’s LSB
(transfer direction specification bit)
Slave
When a start condition is detected
When not used for communication
Slave
When “1” is input by the first byte’s LSB
(transfer direction specification bit)
ACKD0
Detection of ACK
0
ACK was not detected.
1
ACK was detected.
Condition for clearing (ACKD0 = 0)
Condition for setting (ACKD0 = 1)
When a stop condition is detected
At the rising edge of the next byte’s first clock
Cleared by LREL0 = 1
When IICE0 changes from 1 to 0
When RESET is input
After the SDA0 line is set to low level at the
rising edge of the SCL0’s ninth clock