217
CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE
Figure 8-15. Format of Automatic Data Transfer/Reception Control Register
(
μ
PD780058, 780058Y subseries)
Notes 1.
Bits 3 and 4 (TRF and ERR) are read-only bits.
2.
Identify the end of automatic transfer/reception by using TRF instead of CSIIF1. (interrupt request flag)
Cautions 1. When external clock input is selected by clearing bit 1 (CSIM11) of the serial operating mode
register 1 (CSIM1) to 0, clear STRB and BUSY1 of ADTC to 0, 0.
2. When using the P23/STB/TxD1 and P24/BUSY/RxD1 pins in the asynchronous serial interface
(UART) mode of serial interface channel 2, the busy control option and busy & strobe control
option are invalid.
Remark
×
: don’t care
7
6
5
4
3
2
Symbol
1
0
FF69H
BUSY0
ADTC
BUSY1
TRF
STRB
ERR
ERCE
ARLD
RE
Address
At reset
R/W
00H
R/W
Note 1
BUSY1
Controls busy input
0
Does not use busy input
1
Enables busy input (active high)
BUSY0
×
0
1
Enables busy input (low active)
1
R/W
STRB
Controls strobe output
0
Disables strobe output
1
Enables strobe output
R/W
TRF
Status of automatic transfer/reception function
Note 2
0
Detects end of automatic transfer/reception (0 when
automatic transfer/reception is stopped or when ARLD
= 0)
1
Automatic transfer/reception in progress (1 when SIO1
is written)
R
ERR
Detects error of automatic transfer/reception function
0
No error on automatic reception (0 when 1 is written to
SIO1)
1
Error on automatic transfer/reception
R
ERCE
Controls error check of automatic transfer/reception
function
0
Disables error check on automatic transfer/reception
1
Enables error check on automatic transfer/reception
(only when BUSY1 = 1)
R/W
ARLD
Selects operation mode of automatic transfer/
reception function
0
Single mode
1
Repetitive mode
R/W
RE
Controls reception of automatic transfer/reception
function
0
Disables reception
1
Enables reception
R/W