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參數(shù)資料
| 型號： | μPD75P3018A |
| 廠商： | NEC Corp. |
| 英文描述： | 4 Bit Single Chip Microcontrollers(4位單片微控制器) |
| 中文描述： | 4位單片微控制器（4位單片微控制器） |
| 文件頁數(shù)： | 36/60頁 |
| 文件大?。?/td> | 337K |
| 代理商： | ΜPD75P3018A |
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μPD75P3018A
36
Subsystem Clock Oscillation Circuit Characteristics (T
A
= –40 to +85 °C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended Constants
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Crystal
resonator
Oscillation frequency
(f
XT
)
32
32.768
35
kHz
Note 1
Oscillation
stabilization time
V
DD
= 4.5 to 5.5 V
1.0
2
s
Note 2
10
External
clock
XT1 input frequency
(f
XT
)
32
100
kHz
Note 1
XT1 input high-/
low-level widths
(t
XTH
, t
XTL
)
5
15
μs
Notes
only. For the instruction execution time, refer to AC Characteristics.
2. The oscillation stabilization time is the time required for oscillation to be stabilized after V
DD
has been applied.
Caution
When using the subsystem clock oscillation circuit, wire the portion enclosed in the broken line in the
above figure as follows to prevent adverse influence due to wiring capacitance:
Keep the wiring length as short as possible.
Do not cross the wiring with other signal lines.
Do not route the wiring in the vicinity of a line through which a high alternating current flows.
Always keep the ground point of the capacitor of the oscillation circuit at the same potential as V
Do not ground to a power supply pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
DD
.
The subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and
is more susceptible to noise than the main system clock oscillation circuit. Therefore, exercise utmost
care in wiring the subsystem clock oscillation circuit.
XT1
XT2
C3
C4
R
V
DD
XT1
XT2
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