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參數(shù)資料
| 型號(hào)： | μPD705100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Microprocessor(32 位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 27/81頁(yè) |
| 文件大?。?/td> | 441K |
| 代理商： | ΜPD705100 |
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CHAPTER 3 ADDRESS SPACE
CHAPTER 3 ADDRESS SPACE
3.1 MEMORY SPACE
The V830 uses four chip select/address pins and 26 address bus pins to represent a 32-bit address. When
the chip select function is used, a 256M-byte image space is created as three spaces and a 32M-byte image
space is created as one space. When the chip select function is not used, a 4G-byte linear address space
is created.
Area 40000000H-7FFFFFFFH in the memory space is reserved as an uncachable area. When this area
is accessed, the cache function is not effective. For all other areas, the cache function is effective.
Within the memory space, built-in instruction RAM and built-in data RAM are mapped. By accessing these
areas, an instruction can be fetched and data loaded/stored within one cycle (internal clock) without activating
a bus cycle externally. Data in the built-in instruction RAM, however, cannot be accessed by using the load/
store instructions. Nor can instructions be fetched from the built-in data RAM. These built-in RAMs are mapped
to the cachable area; however, they are not cached.
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