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CHAPTER 11 PWM UNIT
11.4 Operations
11.4.1 Basic operations
When outputting the PWMn pulse, after setting the data required for the PWPR register and PWMn register, the
PWMEn bits of the PWMC register should be set (1). This resets the TMPn, and the PWMn output is set to the active
level, and the data is transmitted from the PWMn to the CMPn in the first overflow. After that, when the TMPn and
CMPn coincide, the PWMn output becomes inactive. This is repeated and the active level PWMn signal specified
by the ALVn bits of the PWMC register from the PWMn pin is output.
When the PWMEn bits of the PWMC register are cleared (0), the PWMn output unit stops PWMn output
immediately, and the PWMn output becomes the level of ALVn set by the PWMC register.
When the settings of the PWPn0 to PWPn2 bits and PRMn0 and PRMn1 bits are changed while the PWMn signal
is output, the period width and pulse width of the PWMn signal in the changed period cannot be guaranteed.