參數(shù)資料
型號(hào)： μPD703002
廠商： NEC Corp.
英文描述： 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器)
中文描述： 16/32位單片機(jī)微控制器（16/32位單片微控制器）
文件頁(yè)數(shù)： 63/72頁(yè)
文件大小： 528K
代理商： ΜPD703002
63
μ
PD703002
(9) CSI timing
(a) Master mode
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<70>
t
CYSK
Output
250
ns
SCKn high-level width
<71>
t
WSKH
Output
0.5t
CYSK
–20
ns
SCKn low-level width
<72>
t
WSKL
Output
0.5t
CYSK
–25
ns
SIn setup time (to SCKn
↑
)
<73>
t
SSISK
45
ns
SIn hold time (from SCKn
↑
)
<74>
t
HSKSI
0
ns
SOn output delay time
(from SCK0
↓
)
<75>
t
DSKSO
25
ns
SOn output delay time
(from SCK0
↑
)
<76>
t
HSKSO
0.5t
CYSK
–5
ns
Caution
When the internal clock is selected as the serial clock, set f to 8 MHz or lower if specifying
φ
/
2, and set
φ
to 16 MHz or lower if specifying
φ
/4 (
φ
= internal operation clock frequency). To select
a higher operating frequency than those indicated above, select the baud rate generator (BRG)
output instead of the internal clock.
(b) Slave mode
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<70>
t
CYSK
Input
250
ns
SCKn high-level width
<71>
t
WSKH
Input
70
ns
SCKn low-level width
<72>
t
WSKL
Input
70
ns
SIn setup time (to SCKn
↑
)
<73>
t
SSISK
10
ns
SIn hold time (from SCKn
↑
)
<74>
t
HSKSI
15
ns
SOn output delay time
(from SCKn
↓
)
<75>
t
DSKSO
55
ns
SOn output hold time
(from SCKn
↑
)
<76>
t
HSKSO
t
WSKH
ns
Caution
When the internal clock is selected as the serial clock, set f to 8 MHz or lower if specifying
φ
/
2, and set
φ
to 16 MHz or lower if specifying
φ
/4 (
φ
= internal operation clock frequency). To select
a higher operating frequency than those indicated above, select the baud rate generator (BRG)
output instead of the internal clock.
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