參數(shù)資料
型號： μPD4564323
廠商： NEC Corp.
英文描述： 64M-bit Synchronous DRAM(64M 同步動態(tài)RAM)
中文描述： 6400位同步DRAM（6400同步動態(tài)RAM）的
文件頁數(shù)： 1/82頁
文件大?。?/td> 659K
代理商： ΜPD4564323
The information in this document is subject to change without notice.
1997
MOS INTEGRATED CIRCUIT
μ
PD4564323
64M-bit Synchronous DRAM
4-bank, LVTTL
PRELIMINARY DATA SHEET
Document No.
Date Published
Printed in Japan
M12976EJ4V0DS00 (4th edition)
September 1998 NS CP (K)
The mark
shows major revised points.
Description
The
μ
PD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as
524,288 words
×
32 bits
×
4banks.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 86-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
×
32 organization
Byte control by DQM0, DQM1, DQM2 and DQM3
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
Single 3.3 V
±
0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
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