參數(shù)資料
型號： μPD45256163
廠商： NEC Corp.
英文描述： 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
中文描述： 256M位同步DRAM（256M同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 12/84頁
文件大小： 1052K
代理商： ΜPD45256163
12
μ
PD45256441,45256841,45256163
Preliminary Data Sheet
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst write
operation. The first write data in burst mode can input with this command
with subsequent data on following clocks.
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met.
This command sets the burst start address given by the column address.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR refresh operation. The
refresh address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready
for a row activate command.
During t
RC
period (from refresh command to refresh or activate command),
the
μ
PD45256xxx cannot accept any other command.
Fig.4 Column address and
write command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Col.
Fig.5 Column address and read
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Col.
Fig.6 Auto refresh command
Add
A10
BA0, BA1
(Bank select)
/WE
/CAS
/RAS
/CS
CKE
CLK
H
相關(guān)PDF資料
PDF描述
μPD45256441 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
μPD45256841 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
μPD4564163 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
μPD4564441 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
μPD4564841 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
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