參數(shù)資料
型號: μPD4516821A
廠商: NEC Corp.
英文描述: 16M-bit Synchronous DRAM(16M 同步動態(tài)RAM)
中文描述: 1,600位同步DRAM(1,600同步動態(tài)RAM)的
文件頁數(shù): 29/86頁
文件大?。?/td> 904K
代理商: ΜPD4516821A
μ
PD4516421A, 4516821A, 4516161A for Rev. P
29
11. Read/Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after CAS latency, even if the previous
READ operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without
any restriction.
QB1
QB2
QB3
QB4
Hi-Z
Read A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, CAS latency = 2
Read B
QA1
1cycle
11.2 Write to Write Command Interval
During a write cycle, when new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write commnad. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1. Each Write command can be issued in every clock without
any restriction.
DB1
DB2
DB3
DB4
Hi-Z
Write A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, CAS latency = 2
Write B
DA1
1cycle
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