參數(shù)資料
型號: μPD4516421A
廠商: NEC Corp.
英文描述: 16M-bit Synchronous DRAM(16M 同步動態(tài)RAM)
中文描述: 1,600位同步DRAM(1,600同步動態(tài)RAM)的
文件頁數(shù): 22/86頁
文件大?。?/td> 904K
代理商: ΜPD4516421A
μ
PD4516421A, 4516821A, 4516161A for Rev. P
22
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A11 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
CAS latency: A6 through A4
Wrap type
: A3
Burst length : A2 through A0
: A11 through A7
Following mode register programming, no command can be issued before at least 2CLK have elapsed.
CAS Latency
CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before
the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device. The table on page 43
shows the relationship of CAS latency to the clock period and the speed grade of the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing.
The table on the page 24 shows the addressing sequence for each burst length using them. Both sequences support
bursts of 1, 2, 4 and 8. Additionally, sequential sequence supports the full page length.
相關PDF資料
PDF描述
μPD4516821A 16M-bit Synchronous DRAM(16M 同步動態(tài)RAM)
μPD45256163 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
μPD45256441 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
μPD45256841 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
μPD4564163 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
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