
μ
PD30500, 30500A, 30500B
12
Data Sheet U12031EJ4V0DS00
Pin Name
I/O
Function
Int (0:5)
Input
Interrupt.
General-purpose processor interrupt requests whose input statuses can be confirmed by
bits 15 through 10 of cause register.
NMI
Input
Non-maskable interrupt.
Interrupt request that cannot be masked.
ColdReset
Input
Cold reset.
Signal initializing the internal status of the processor. Inactivate this signal in synchroniza-
tion with SysClock.
Reset
Input
Reset.
Signal generating a reset exception, without initializing the internal status of the processor.
Inactivate this signal in synchronization with SysClock.
SysClock
Input
System clock.
Clock input signal to processor.
BigEndian
Input
Endian mode setting.
This signal sets the endian mode of the system interface.
When setting the endian mode with this signal, specify little endian with the data from the
ModeIn pin that is input at reset.
To set the endian mode with the data from the ModeIn pin, fix this signal to 0.
BigEndian
Bit 8 of boot mode
Mode
1
1
0
0
1
0
1
0
—
Big endian
Big endian
Little endian
ModeClock
Output
Boot mode clock.
Successive boot mode data clock output resulting from dividing SysClock by 256.
Modeln
Input
Boot mode data input.
Input of initialization bit stream.
V
DD
Ok
Input
V
DD
and V
DD
IO
Note1
are valid.
Signal indicating that the voltage supplied to the V
R
5000 is reached to the rated level
Note2
for 100 ms or more, and that that status is stabilized. When V
DD
Ok is asserted active, the
V
R
5000 starts an initialization sequence.
V
DD
P
–
PLL V
DD
.
Power supply for internal PLL.
GNDP
–
PLL GND.
Ground for internal PLL.
V
DD
–
V
R
5000
Positive power supply pin (3.3 V)
V
R
5000A
Power supply pin for core (2.5 V)
V
R
5000B
Power supply pin for core (1.8 V)
V
DD
IO
Note1
–
Power supply pin for I/O (3.3 V)
GND
–
Ground pin.
Notes 1.
V
DD
IO is only for V
R
5000A and V
R
5000B.
2.
V
R
5000: V
DD
= 3.135 V
V
R
5000A: V
DD
= 2.375 V, V
DD
IO = 3.135 V
V
R
5000B: V
DD
= 1.7 V, V
DD
IO = 3.135 V