
Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 3 of 4
DS022-3 (v3.0) March 21, 2014
10
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Speed Grade
Units
Description
Symbol
Standard
Min
-8
-7
-6
Output Delay Adjustments
Standard-specific adjustments for output
delays terminating at pads (based on
standard capacitive load, Csl)
TOLVTTL_S2
LVTTL, Slow, 2 mA
4.2
+14.7
ns
TOLVTTL_S4
4 mA
2.5
+7.5
ns
TOLVTTL_S6
6 mA
1.8
+4.8
ns
TOLVTTL_S8
8 mA
1.2
+3.0
ns
TOLVTTL_S12
12 mA
1.0
+1.9
ns
TOLVTTL_S16
16 mA
0.9
+1.7
ns
TOLVTTL_S24
24 mA
0.8
+1.3
ns
TOLVTTL_F2
LVTTL, Fast, 2 mA
1.9
+13.1
ns
TOLVTTL_F4
4 mA
0.7
+5.3
ns
TOLVTTL_F6
6 mA
0.20
+3.1
ns
TOLVTTL_F8
8 mA
0.10
+1.0
ns
TOLVTTL_F12
12 mA
0.0
ns
TOLVTTL_F16
16 mA
–0.10
–0.05
ns
TOLVTTL_F24
24 mA
–0.10
–0.20
ns
TOLVCMOS_2
LVCMOS2
0.10
+0.09
ns
TOLVCMOS_18
LVCMOS18
0.10
+0.7
ns
TOLVDS
LVDS
–0.39
–1.2
ns
TOLVPECL
LVPECL
–0.20
–0.41
ns
TOPCI33_3
PCI, 33 MHz, 3.3 V
0.50
+2.3
ns
TOPCI66_3
PCI, 66 MHz, 3.3 V
0.10
–0.41
ns
TOGTL
GTL
0.6
+0.49
ns
TOGTLP
GTL+
0.7
+0.8
ns
TOHSTL_I
HSTL I
0.10
–0.51
ns
TOHSTL_III
HSTL III
–0.10
–0.91
ns
TOHSTL_IV
HSTL IV
–0.20
–1.01
ns
TOSSTL2_I
SSTL2 I
–0.10
–0.51
ns
TOSSTL2_II
SSTL2 II
–0.20
–0.91
ns
TOSSTL3_I
SSTL3 I
–0.20
–0.51
ns
TOSSTL3_II
SSTL3 II
–0.30
–1.01
ns
TOCTT
CTT
0.0
–0.61
ns
TOAGP
AGP
–0.1
–0.91
ns