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參數(shù)資料
| 型號： | XC18V04PC44C |
| 廠商： | XILINX INC |
| 元件分類： | DRAM |
| 英文描述： | In-System Programmable Configuration PROMs |
| 中文描述： | 512K X 8 CONFIGURATION MEMORY, 20 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大小： | 230K |
| 代理商： | XC18V04PC44C |
R
Figure 5:
Configuring Multiple Devices in Master/Slave Serial Mode
4.7K
4.7K
(See
Note
1)
1
2
3
4
TDO
DOUT
TDI
TMS
TCK
VCCINT
VCCO
DIN
CCLK
DONE
INIT
MODE PINS
Xilinx
FPGA
Master
Serial
VCCINT
D0
VCCO
TDI CLK
TMS CE
TCK CEO
OE/RESET
PROGRAM
TDO
TDI
TMS
TCK
DIN
CCLK
DONE
INIT
MODE PINS
Xilinx
FPGA
Slave
Serial
PROGRAM
CF
TDO
GND
For Mode pin connections and DONE pin pullup value, refer to appropriate FPGA data sheet.
For compatible voltages, refer to the appropriate FPGA data sheet.
XC18V00
Cascaded
PROM
TDI
TMS
TCK
TDO
J1
DS026_08_061003
VCCINT
VCCO
VCCO
VCCINT
D0
VCCO
TDI CLK
TMS CE
TCK CEO
OE/RESET
CF
TDO
GND
XC18V00
First
PROM
VCCO
(See Note 2)
(See Note 2)
(See Note 2)
Notes:
1
2
Figure 6:
Configuring Multiple Virtex-II Devices with Identical Patterns in Master/Slave or Serial/SelectMAP Modes
4.7K
4.7K
1
2
3
4
TDO
TDI
TMS
TCK
VCCINT
VCCO
D[0:7]
CCLK
DONE
INIT
MODE PINS
Xilinx
Virtex-II
FPGA
Master
Serial/
SelectMAP
VCCINT
D[0:7]
VCCO
TDI CLK
TMS CE
TCK CEO
OE/RESET
PROGRAM
TDO
TDI
TMS
TCK
**D[0:7]
CCLK
DONE
INIT
MODE PINS
Xilinx
Virtex-II
FPGA
Slave
Serial/
SelectMAP
PROGRAM
CF
TDO
GND
For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
For compatible voltges, refer to the appropriate FPGA data sheet.
Master/Slave Serial Mode does not require D[1:7] to be connected.
XC18V00
Cascaded
PROM
TDI
TMS
TCK
TDO
J1
DS026_09_051003
VCCINT
VCCO
VCCO
VCCINT
D[0:7]
VCCO
TDI CLK
TMS CE
TCK CEO
OE/RESET
CF
TDO
GND
XC18V00
First
PROM
VCCO
Notes:
1
2
3
(2)
(2)
(2)
(1)
(2)
(1)
(3)
(3)
(3)
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相關代理商/技術參數(shù) |
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|---|---|
| XC18V04-PC44C | 制造商:Xilinx 功能描述: |
| XC18V04PC44C0100 | 制造商:Xilinx 功能描述: |
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| XC18V04PC44C0936 | 制造商:Xilinx 功能描述:XLXXC18V04PC44C0936 IC SYSTEM GATE |
| XC18V04PC44C1 | 制造商:Xilinx 功能描述: |
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