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參數(shù)資料
| 型號(hào)： | XC17V02PC44I |
| 廠商： | XILINX INC |
| 元件分類： | DRAM |
| 英文描述： | GIGATRUE 550 CAT6 BLACK STRANDED BULK 1000FT |
| 中文描述： | 2M X 1 CONFIGURATION MEMORY, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 114K |
| 代理商： | XC17V02PC44I |
DS073 (v1.0) July 26, 2000
Advance Product Specification
R
Figure 3:
(a) Master Serial Mode (b) Virtex SelectMAP Mode
(dotted lines indicates optional connection)
PROGRAM
DIN
CCLK
INIT
DONE
First
PROM
DATA
CEO
BUSY
BUSY
DATA
CLK
CE
OE/RESET
OPTIONAL
Slave FPGAs
with identical
configurations
Vcc
FPGA
(Low Resets the Address Pointer)
VCC VCCO
OPTIONAL
Daisy-chained
FPGAs with
different
configurations
DOUT
Modes*
Vcco
VIRTEX
Select MAP
BUSY
BUSY
CS
WRITE
INIT
D[0:7]
CCLK
DONE
CLK
Virtex Select MAP Mode, XC17V16 and XC17V08 only.
D[0:7]
CE
OE/RESET
XC17Vxx
Modes***
3.3V
External Osc
CEO
4.7K
VCC
4.7K
VCC
**
**
V
CC
V
CCO
V
CC
V
CCO
V
CC
1K
I/O*
Master Serial Mode
8
I/O*
1K
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
**Virtex, Virtex-E is 300 ohms, all others are 4.7K.
***For Mode pin connections, refer to the appropriate FPGA data sheet.
DS073_03_072600
*For Mode pin connections, refer to the appropriate FPGA data sheet.
**Virtex, Virtex-E is 300 ohms, all others are 4.7K.
Cascaded
PROM
CLK
CE
OE/RESET
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC17V02SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:XC17V00 Series Configuration PROM |
| XC17V02SO20C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROM |
| XC17V02SO20I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROM |
| XC17V02V08C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROM |
| XC17V02V08I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROM |
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