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參數(shù)資料
| 型號(hào)： | XC17V02PC44I |
| 廠商： | XILINX INC |
| 元件分類： | DRAM |
| 英文描述： | GIGATRUE 550 CAT6 BLACK STRANDED BULK 1000FT |
| 中文描述： | 2M X 1 CONFIGURATION MEMORY, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 114K |
| 代理商： | XC17V02PC44I |
DS073 (v1.0) July 26, 2000
Advance Product Specification
1-800-255-77781
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
Simple interface to the FPGA; configurable to use a
one user I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Supports fast configuration
Low-power CMOS Floating Gate process
3.3V supply voltage
Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Dual configuration modes for the XC17V16 and
XC17V08
-
Serial slow/fast configuration (up to 33 MHz)
-
Parallel (up to 264 MHz)
Guaranteed 20 year life data retention
Description
Xilinx introduces the high-density XC17V00 family of config-
uration PROMs which provide an easy-to-use, cost-effec-
tive method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
When the FPGA is in SelectMAP mode, an external oscilla-
tor will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the PROMs DATA (D0-D7) pins. The data will
be clocked into the FPGA on the following rising edge of the
CCLK. SelectMAP does not utilize a Length Count, so a
free-running oscillator may be used. See
Figure 3
.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
0
XC17V00 Series Configuration
PROM
DS073 (v1.0) July 26, 2000
0
8
Advance Product Specification
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC17V02SO20C | GIGATRUE 550 CAT6 PATCH 1 FT, SNAGLESS, PURPLE |
| XC17V04SO20C | XC17V00 Series Configuration PROM |
| XC17V04SO20I | XC17V00 Series Configuration PROM |
| XC17V04V08I | XC17V00 Series Configuration PROM |
| XC17V08PC20C | XC17V00 Series Configuration PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC17V02SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:XC17V00 Series Configuration PROM |
| XC17V02SO20C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROM |
| XC17V02SO20I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROM |
| XC17V02V08C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROM |
| XC17V02V08I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROM |
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