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參數(shù)資料
| 型號(hào)： | WED3DG7217V7D2 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 454K |
| 代理商： | WED3DG7217V7D2 |
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15459
WED3DG7217V-D2
(Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, Vout
-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Storage Temperature
TSTG
-55 ~ +150
°C
Power Dissipation
PD
9
W
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
VDD
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0 VDDQ+0.3 V
1
Input Low Voltage
VIL
-0.3
0.8
V
2
Output High Voltage
VOH
2.4
V
IOH= -2mA
Output Low Voltage
VOL
0.4
V
IOL= -2mA
Input Leakage Current
ILI
-10
10
A
3
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State
outputs.
CAPACITANCE
(TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4V 6200mV)
Parameter
Symbol
Min
Max
Unit
Input Capacitance (A0-A12)
CIN1
-
50
pF
Input Capacitance (RAS,CAS,WE)
CIN2
-
50
pF
Input Capacitance (CKE0)
CIN3
-
50
pF
Input Capacitance (CLK0)
CIN4
-
25
pF
Input Capacitance (CS0,CS2)
CIN5
-
30
pF
Input Capacitance (DQM0-DQM7)
CIN6
-
10
pF
Input Capacitance (BA0-BA1)
CIN7
-
50
pF
Data input/output capacitance (DQ0-DQ63)
Cout
-
12
pF
Data input/output capacitance (CB0-CB7)
Cout1
-
12
pF
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