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參數(shù)資料
| 型號： | WED3DG6432V7D1SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, ZMA144 |
| 封裝： | ROHS COMPLIANT, SODIMM-144 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 245K |
| 代理商： | WED3DG6432V7D1SG |
WED3DG6432V-D1
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
January 2006
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(VCC = 3.3V, TA = 0°C to +70°C)
AC Characteristics
Symbol
75
7
10
Units
Notes
Parameter
Min
Max
Min
Max
Min
Max
ns
27
Access time from CLK
(positive edge)
CL = 3
tAC(3)
5.4
6
ns
CL = 2
tAC(2)
5.4
6
ns
Address hold time
tHC
0.8
1
ns
Address setup time
tAS
1.5
2
ns
CLK high-level width
tCH
2.5
3
ns
CLK low-level width
tCL
2.5
3
ns
Clock cycle time
CL = 3
tCK(3)
7
7.5
8
ns
24
CL = 2
tCK(2)
7.5
10
ns
24
CKE hold time
tCKH
0.8
1
ns
CKE setup time
tCKS
1.5
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
0.8
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
2
ns
Data-in hold time
tDH
0.8
1
ns
Data-in setup time
tDS
1.5
2
ns
Data-out high-impedance
time
CL = 3
tHZ(3)
5.4
6
ns
10
CL = 2
tHZ(2)
5.4
6
ns
10
Data-out low-impedance time
tLZ
111
ns
Data-out hold time (load)
tOH
333
ns
Data-out hold time (no load)
tOHN
1.8
ns
28
Active to Active command
tRAS
37
120,000
44
120,000
50
120,000
ns
32
Active to Active command period
tRC
60
66
70
ns
Active to Read or Write delay
tRCD
15
20
ns
Refresh period
tREF
64
ns
Auto Refresh period
tRCF
66
70
ns
Precharge command period
tRP
15
20
ns
Active bank a to Active bank b command
tRRD
14
15
20
ns
Transition time
tT
0.3
1.2
0.3
1.2
0.3
1.2
ns
7
Write recovery time
tWR
1 CKE +
7 ns
1 CKE +
7.5 ns
1 CKE +
7 ns
ns
24
14
15
ns
25
Exit Self Refresh to Active command
tXSR
67
75
80
ns
20
NOTE:
AC specication is based on
MICRON components. Other DRAM manufactures specication may be different.
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