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參數(shù)資料
| 型號(hào)： | WED3DG6366V75D2 |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 169K |
| 代理商： | WED3DG6366V75D2 |
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WED3DG6466V-D2
May 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Notes
1.
All voltages referenced to VSS.
2.
This parameter is sampled. VCC, VCCQ = +3.3V; TA = 25°C; pin under test biased
at 1.4V; f = 1 MHz.
3.
IDD is dependent on output loading and cycle rates. Specied values are obtained
with mini-mum cycle time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6.
An initial pause of 100μs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.)
The two AUTO REFRESH command wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
7.
AC characteristics assume tT = 1ns.
8.
In addition to meeting the transition rate specication, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner.
9.
Outputs measured at 1.5V with equivalent load:
Q
50pF
10.
tHZ denes the time at which the output achieves the open circuit condition; it is
not a reference to VOH or VOL. The last valid data element will meet tOH before
going High-Z.
11.
AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.
12.
Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13.
IDD specications are tested after the device is properly initialized.
14.
Timing actually specied by tCKS; clock(s) specied as a reference only at
minimum cycle rate.
15.
Timing actually specied by tWR plus tRP; clock(s) specied as a reference only at
minimum cycle rate.
16.
Timing actually specied by tWR.
17.
Required clocks are specied by JEDEC functionality and are not dependent on
any timing parameter.
18.
The IDD current will increase or decrease proportionally according to the amount
of frequency alteration for the test condition.
19.
Address transitions average one transition every two clocks.
20.
CLK must be toggled a minimum of two times during this period.
21.
Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 7.5.
22.
VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse
width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL
(MIN) = -2V for a pulse width ≤ 3ns.
23.
The clock frequency must remain constant (stable clock is dened as a signal
cycling within timing constraints specied for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24.
Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for 7;
7.5ns for 7.5 and 7.5ns for 10 after the rst clock delay, after the last WRITE is
executed. May not exceed limit set for precharge mode.
25.
Precharge mode only.
26.
JEDEC and PC133, PC100 specify three clocks.
27.
tAC for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28.
Parameter guaranteed by design.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| WED3DG6366V7D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -64Mx64, SDRAM UNBUFFERED |
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| WED3DG637V7D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64MB- 8Mx64 SDRAM UNBUFFERED |
| WED3DG638V10D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64MB- 8Mx64 SDRAM UNBUFFERED |
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