
U632H64
6
August 15, 2006
STK Control #ML0047
Rev 1.1
(15)
t
su(A)
t
su(A-WH)
L- to H-level
undefined
H- to L-level
i:
j:
If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
E or W must be V
IH
during address transition.
Write Cycle #1: W-controlled
j
Write Cycle #2: E-controlled
j
t
h(D)
Ai
E
W
DQi
Input
DQi
Output
t
cW
t
su(E)
t
h(A)
t
w(W)
t
su(D)
t
dis(W)
t
en(W)
Address Valid
Input Data Valid
High Impedance
(12)
(16)
(13)
(19)
(20)
(23)
(21)
t
su(A)
t
h(D)
Ai
E
W
DQi
Input
DQi
Output
t
cW
t
w(E)
t
h(A)
t
su(D)
Address Valid
Input Data Valid
t
su(W)
(12)
(18)
(21)
(20)
(19)
(17)
(22)
Previous Data Valid
High Impedance
(15)
(14)