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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
TYPICAL DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
TPA3100D2
SLOS469D–OCTOBER 2005–REVISED FEBRUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
UNIT
V
CC
Supply voltage
AVCC, PVCC
SHUTDOWN, MUTE
GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,
SYNC
–0.3 V to 30 V
–0.3 V to V
CC
+ 0.3 V
V
I
Input voltage
–0.3 V to VREG + 0.5 V
Continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range
(2)
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Load Resistance
Human body model
(3)
(all pins)
Electrostatic discharge
Machine model
(4)
(all pins)
Charged-device model
(5)
(all pins)
See Dissipation Rating Table
–40
°
C to 85
°
C
–40
°
C to 150
°
C
–65
°
C to 150
°
C
260
°
C
3.2
Minimum
±
2 kV
±
200 V
±
500 V
T
A
T
J
T
stg
R
Load
(1)
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The TPA3100D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs
SCBA017D
and
SLUA271
for more information about using the QFN thermal pad. See TI Technical
Briefs
SLMA002
for more information about using the HTQFP thermal pad.
In accordance with JEDEC Standard 22, Test Method A114-B.
In accordance with JEDEC Standard 22, Test Method A115-A
In accordance with JEDEC Standard 22, Test Method C101-A
(2)
(3)
(4)
(5)
PACKAGE
48-pin RGZ (QFN)
48-pin PHP (HTQFP)
T
A
≤
25
°
C
4.63 W
5 W
DERATING FACTOR
37 mW/
°
C
(1)
40 mW/
°
C
(2)
T
A
= 70
°
C
2.96 W
3.2 W
T
A
= 85
°
C
2.41 W
2.6 W
(1)
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs
SCBA017D
and
SLUA271
for more information about
using the QFN thermal pad.
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs
SLMA002
for more information about using the
HTQFP thermal pad.
(2)
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
10
MAX
26
UNIT
V
V
CC
PVCC, AVCC
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
SYNC
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
SYNC
SHUTDOWN, V
I
= V
CC
, V
CC
= 24 V
MUTE, V
I
= V
CC
, V
CC
= 24 V
GAIN0, GAIN1, MSTR/SLV, SYNC, V
I
= VREG,
V
CC
= 24 V
V
IH
High-level input voltage
2
V
V
IL
Low-level input voltage
0.8
V
125
75
I
IH
High-level input current
μA
2
2
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