
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet, Rev. 1
October 2000
138
Lucent Technologies Inc.
TMUX Functional Description
(continued)
TMUX Register Descriptions
(continued)
Table 45. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW)
(continued)
Address
Bit
Name
Function
Reset
Default
0
0x40009
15
TMUX_RSFB3D3
Receive Path Signal Fail BER Algorithm Delta.
This delta bit
indicates a change of state for the signal fail BER algorithm
state bit TMUX_RSFB32 (Table 54) at the path level for port 3.
Only port 1 information is valid in AU-4 mode and in STS-1
mode. The mask bit is TMUX_RSFB3M3 (Table 49).
Receive Path Signal Degrade BER Algorithm Delta.
This
delta bit indicates a change of state for the signal fail BER algo-
rithm state bit TMUX_RSDB32 (Table 54) at the path level for
port 3. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RSDB3M3 (Table 49).
TMUX_RUNEQPE3
Receive Path Unequipped Event.
This event bit indicates that
the current value of the received C2 (signal label) byte,
TMUX_C2MON3[7:0] (Table 66), has a value 0x00, indicating
unequipped payload for port 3. Only port 1 information is valid
in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RUNEQPM3 (Table 49).
TMUX_RPLMPE3
Receive Path Payload Label Mismatch Event.
This event bit
indicates that the current value of the received C2 (signal label)
byte, TMUX_C2MON3[7:0], differs from the expected C2 value,
TMUX_C2EXP3[7:0] (Table 62) for port 3. Only port 1 informa-
tion is valid in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RPLMPM3 (Table 49).
TMUX_RN1MOND3
Receive N1 Monitor Delta.
This delta bit indicates a change in
state in TMUX_N1MON3[7:0] (Table 66). The N1 current value
is updated when a consecutive and consistent value is
detected in the incoming N1 byte for TMUX_CNTDN1[3:0]
(Table 61) frames on port 3. Only port 1 information is valid in
AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RN1MONM3 (Table 49).
TMUX_RK3MOND3
Receive K3 Monitor Delta.
This delta bit indicates a change in
state in TMUX_K3MON3[7:0] (Table 66), which is updated
when a consecutive and consistent value is detected in the
incoming K3 byte for TMUX_CNTDK3[3:0] (Table 61) frames
on port 2. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RK3MONM3 (Table 49).
14
TMUX_RSDB3D3
0
13
0
12
0
11
0
10
0