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參數(shù)資料
| 型號(hào)： | SY87739L |
| 英文描述： | High Efficient Rectifier Diodes |
| 中文描述： | 協(xié)議透明3.3 10MHz至729MHz分?jǐn)?shù)N合成器 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | SY87739L |
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SY87700L
2
Micrel
PLLSP
TCLKN
18
11
PLLSN
CLKSEL
17
12
GND
PLLRP
16
13
GND
PLLRN
15
14
1
VCCA
LFIN
DIVSEL1
RDINP
RDINN
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
N/C
28 VCC
CD
DIVSEL2
RDOUTP
RDOUTN
VCCO
RCLKP
RCLKN
VCCO
TCLKP
27
26
25
24
23
22
21
20
19
2
3
4
5
6
7
8
9
10
Top View
SOIC
Z28-1
PIN CONFIGURATION
PIN DESCRIPTIONS
INPUTS
RDINP, RDINN [Serial Data Input]
Differential PECL
These built-in line receiver inputs are connected to the
differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data
(RDOUT) information. The incoming data rate can be within
one of five frequency ranges depending on the state of the
FREQSEL pins. See “Frequency Selection” Table.
REFCLK [Reference Clock]
TTL inputs
This input is used as the reference for the internal
frequency synthesizer and the "training" frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN inputs.
CD [Carrier Detect]
PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW the
data on the inputs RDIN will be internally forced to a constant
LOW, the data outputs RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW and the clock
recovery PLL forced to look onto the clock frequency
generated from REFCLK.
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
RDINP
RDINN
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
NC
RDOUTP
RDOUTN
VCCO
RCLKP
RCLKN
VCCO
TCLKP
TCLKN
9
10
11
12
13
14
15
16
C
P
P
G
G
G
P
P
32
31
30
29
28
27
26
25
D
C
V
V
V
V
L
D
Top View
EPAD-TQFP
H32-1
FREQSEL1, ..., FREQSEL3 [Frequency Select]
TTL Inputs
These inputs select the output clock frequency range as
shown in the
“
Frequency Selection
”
Table.
DIVSEL1, DIVSEL2 [Divider Select]
TTL Inputs
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in the
“
Reference Frequency Selection
”
Table.
CLKSEL [Clock Select]
TTL Inputs
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs.
OUTPUTS
LFIN [Link Fault Indicator]
TTL Output
This output indicates the status of the input data stream
RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data
stream. LFIN will go HIGH if CD is HIGH and RDIN is within
the frequency range of the Receive PLL (1000ppm). LFIN
is an asynchronous output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87739L_07 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROTOCOL TRANSPARENT 3.3V 10MHz to 729MHz FRACTIONAL-N SYNTHESIZER |
| SY87739L_11 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Protocol Transparent, 3.3V, 10MHz to 729MHz, Fractional-N Synthesizer |
| SY87739LHG | 功能描述:IC SYNTHESIZER FRACT 3.3V 32TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:AnyClock® 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY87739LHI | 功能描述:IC SYNTHESIZER FRACT 3.3V 32TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:AnyClock® 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY87739LHITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROTOCOL TRANSPARENT 3.3V 10MHz to 729MHz FRACTIONAL-N SYNTHESIZER |
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