參數(shù)資料
型號(hào)： STP20NM60FP
廠商： 意法半導(dǎo)體
英文描述： N-CHANNEL 600V - 0.25ohm - 20A TO-220/FP/D2PAK/I2PAK MDmesh?Power MOSFET
中文描述： N溝道600V的- 0.25ohm - 20A條TO-220/FP/D2PAK/I2PAK的MDmesh？功率MOSFET
文件頁(yè)數(shù)： 1/20頁(yè)
文件大?。?/td> 221K
代理商： STP20NM60FP
DATA SHEET
1
STP2000QFP
Master I/O
32-bit SBus Master I/ O Controller
D
ESCRIPTION
The STP2000 Master I/ O Controller is an integrated SBus master device with built-in standard I/ O capabili-
ties for general purpose computing or embedded applications. The STP2000 directly interfaces the CPU
through the system bus, SBus, to three major I/ O channels for peripherals. The I/ O channels include SCSI-II,
ethernet and a parallel port. Together, with the STP2001 Slave I/ O Controller, it provides a complete I/ O
subsystem.
The STP2000 SBus interface is a 32-bit interface that supports both DMA and slave modes. There is data buff-
ering and flow control on each of the I/ O channels. Each channel has access to the SBus through the controller
which is capable of DMA transfers of up to 32-byte bursts. The SBus slave port is used mostly for status and
control.
The STP2000 incorporates an ethernet controller, a Fast 8-bit SCSI-II controller, and a Centronics parallel port
controller in a single package. The SCSI-II channel directly drives external peripherals. The ethernet channel
can be connected to an external transceiver chip that supports twisted pair ethernet or AUI ethernet. The par-
allel port channel can be routed to external transceivers.
Features
Benefits
Single-chip solution to standard SPARC DVMA devices
Compatible with microSPARC, SuperSPARC and any
SBus based system
Supports concurrent 10 MByte/sec SCSI transfers,
1.25 MByte/sec Ethernet transfers, and 4 MByte/sec
Parallel Port transfers
Direct master/slave SBus interface
JTAG internal and boundary SCAN logic
160-pin PQFP packaging
IC is also available from NCR Corp. (PN - NCR89C100)
Saves cost, power, board space, and weight
Standard low-cost solution
Improved system performance
Improved system performance
Improved chip and board level testability
Cost effective packaging
Second source
July 1997
This Material Copyrighted by Its Respective Manufacturer
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